module dvfs_controller #(
  parameter TEMP_THRESHOLD = 85 // 温度阈值(℃)
)(
  input  wire         clk,
  input  wire         rst_n,
  input  wire [7:0]   temp_sensor,
  input  wire [15:0]  workload_counter,
  output reg  [3:0]   voltage_level,
  output reg  [7:0]   clock_divider
);

  // 工作模式定义
  typedef enum {
    HIGH_PERF,
    BALANCED, 
    POWER_SAVE
  } mode_t;

  mode_t current_mode;
  
  // 控制算法
  always @(posedge clk) begin
    if (temp_sensor > TEMP_THRESHOLD) begin
      // 过热保护：降频降压
      voltage_level <= 4'h8;  // 0.8V
      clock_divider <= 8'h3;  // 原始频率/4
      current_mode <= POWER_SAVE;
      
    end else case (current_mode)
      HIGH_PERF:
        if (workload_counter < 50) begin
          voltage_level <= 4'h9;  // 0.9V
          clock_divider <= 8'h1;  // 全速
          current_mode <= BALANCED;
        end
        
      BALANCED:
        if (workload_counter > 200) begin
          voltage_level <= 4'hA;  // 1.0V
          clock_divider <= 8'h0;  // 超频模式
          current_mode <= HIGH_PERF;
        end else if (workload_counter < 20) begin
          voltage_level <= 4'h7;  // 0.7V
          clock_divider <= 8'h7;  // 低频
          current_mode <= POWER_SAVE;
        end
        
      POWER_SAVE:
        if (workload_counter > 100) begin
          voltage_level <= 4'h9;
          clock_divider <= 8'h1;
          current_mode <= BALANCED;
        end
    endcase
  end

endmodule